1. Field
The present invention relates to systems, and, more particularly, to bus and device access protocols within systems.
2. Description of the Related Art
In systems such as multi-master systems on chip (SoC), a slave device such as an SRAM or Flash memory controller must properly and efficiently support the interface protocol expectations of each potential master. In traditional platform-based designs, different masters may have different expectations on how burst transfers with errors are terminated. For example, direct memory access (DMA) masters and certain central processing units (CPU's) expect for a burst transfer to be aborted once an error is signaled on any beat of a burst transfer, whereas other CPU designs expect for the burst to continue in spite of the error signaling for a particular beat. This presents an issue for the memory controller. Traditional techniques use multiple protocols at higher levels than that of the MAC layer (hardware level). Such techniques do not resolve the issue of supporting bus transfers or multiple master protocols. Improved techniques of designing and implementing memory controllers are therefore desirable.